Objective VHDL provides no predefined mechanism supporting polymorphism of entity objects.
But of course, something like entity polymorphism can be emulated if it is modeled explicitly.
Assume a memory controller which gets read(address) requests via the address bus. Depending on the address the memory_controller forwards this request to a RAM_- or ROM_controller.
The original sender of the read(address) request needs not to distinguish whether to send the request to the RAM or ROM.
But such emulation of polymorphism is no real polymorphism. The binding of objects to method calls takes place at compilation time. Furthermore the binding of the objects to the method calls is done manually and not automatically.
